Assembly Language

Assembly language uses human-readable mnemonics to represent machine code instructions. An assembler performs a one-to-one translation of each mnemonic into the corresponding binary machine code instruction for the target processor.

AQA assembly notation used in exam questions:

• Rn refers to a general-purpose register (R0, R1, R2, …)
• #n denotes an immediate operand (the literal value n)
• n without # is a direct address (the value at memory address n)

LOAD copies data from memory (or a literal) into a register.

LDR R1, 200      ; R1 ← contents of memory address 200 (direct)
LDR R1, #25     ; R1 ← 25 (immediate — load the value 25 itself)

STORE copies data from a register into memory.

STR R1, 200     ; memory[200] ← R1

The processor cannot operate on data while it is in memory — it must be loaded into a register first. Results must be stored back to memory to persist after the program ends.

ADD R1, R2, R3      ; R1 ← R2 + R3
ADD R1, R2, #10     ; R1 ← R2 + 10  (immediate)

SUB R1, R2, R3      ; R1 ← R2 − R3
SUB R1, R2, #5      ; R1 ← R2 − 5

Results are stored in the destination register (first operand). The status register flags (zero, carry, negative) are updated after arithmetic operations. Conditional branches then test these flags.

Worked examples:

Instruction	Before	After
ADD R1, R2, #10	R2=5	R1=15
SUB R1, R2, R3	R2=20, R3=7	R1=13
SUB R0, R0, #1	R0=1	R0=0, zero flag set

COMPARE subtracts two values and sets the status register flags — without storing the result.

CMP R1, R2       ; set flags based on R1 − R2 (result discarded)
CMP R1, #0       ; compare R1 with zero

CMP is used exclusively to set flags for a subsequent conditional branch.

BRANCH instructions:

Mnemonic	Condition	When executed
B label	Unconditional	Jump to label
BEQ label	Equal (zero flag set)	Jump if last CMP result was 0
BNE label	Not equal	Jump if last CMP result was not 0
BGT label	Greater than	Jump if R1 > R2 in last CMP
BLT label	Less than	Jump if R1 < R2 in last CMP

Branch instructions overwrite the Program Counter with the target address, redirecting execution.

These instructions apply Boolean operations bit by bit to each corresponding bit of the operands.

AND R1, R2, R3    ; R1 ← R2 AND R3 (bitwise)
ORR R1, R2, R3   ; R1 ← R2 OR R3
EOR R1, R2, R3   ; R1 ← R2 XOR R3 (Exclusive OR)
MVN R1, R2       ; R1 ← NOT R2 (bitwise invert — "Move Negative")

Common uses:

• AND with a mask to isolate specific bits: AND R1, R1, #0b00001111 keeps only the lower 4 bits
• ORR to set specific bits to 1 without affecting others
• EOR to toggle specific bits
• MVN to flip all bits (two's complement negation requires MVN + ADD #1)

Shift operations move all bits left or right within a register.

LSL R1, R2, #n    ; R1 ← R2 shifted left n bits (Logical Shift Left)
LSR R1, R2, #n    ; R1 ← R2 shifted right n bits (Logical Shift Right)

Effect on values (unsigned):

Operation	Effect	Example (8-bit)
Left shift by 1	Multiply by 2	0000 0101 (5) → 0000 1010 (10)
Left shift by 2	Multiply by 4	0000 0101 (5) → 0001 0100 (20)
Right shift by 1	Integer divide by 2	0000 1010 (10) → 0000 0101 (5)

Bits shifted out are discarded; zeros fill vacated positions (logical shift).

HALT    ; stop execution

HALT terminates the program. The processor stops fetching and executing instructions.

Why HALT is necessary: without a HALT instruction, the processor continues into the next memory location after the program, executing whatever binary data happens to be there as if it were instructions. This produces undefined, often catastrophic behaviour — corrupted data, crashes, or security vulnerabilities. Every well-formed assembly program ends with HALT (or equivalent: RET for subroutine return, SWI for operating system service call).

In operating system terms, HALT typically triggers a software interrupt that returns control to the OS process scheduler rather than literally stopping the processor. The processor then executes the next scheduled process.

Sum of 1 to n (n stored at address 100, result to address 101):

LDR R0, 100      ; R0 ← n
LDR R1, #0       ; R1 ← 0 (sum accumulator)
LDR R2, #0       ; R2 ← 0 (counter)
LOOP:
  CMP R2, R0     ; compare counter with n
  BGT END        ; if counter > n, exit loop
  ADD R1, R1, R2 ; sum += counter
  ADD R2, R2, #1 ; counter++
  B LOOP         ; repeat
END:
  STR R1, 101    ; store result
  HALT

1. Confusing LOAD and STORE direction

LDR moves data from memory into a register. STR moves data from a register into memory. The destination register comes first in LDR. The source register comes first in STR.

2. Forgetting COMPARE before a conditional branch

Conditional branches check the status register flags. Those flags are set by CMP (or the last arithmetic instruction). A conditional branch without a preceding CMP may jump based on stale flags from a previous operation.

3. Treating a shift as a multiplication instruction

Shifts multiply/divide by powers of 2 only, and only for non-negative values (logical shift discards overflow bits). They are not equivalent to a general multiply instruction — LSL #3 is efficient only if you specifically need to multiply by 8.

4. Confusing EOR and OR for toggling

ORR sets bits to 1 (cannot clear). EOR toggles bits — bits that are 1 in the mask flip; bits that are 0 in the mask stay unchanged. To toggle bit 3: EOR R1, R1, #0b00001000.