Processor Components and the Fetch-Execute Cycle

The processor (CPU) contains several functional units:

Component	Role
ALU (Arithmetic Logic Unit)	Performs arithmetic (+, −, ×, ÷) and logical operations (AND, OR, NOT, XOR, shifts, comparisons)
Control Unit (CU)	Manages the fetch-execute cycle; decodes instructions; generates control signals to coordinate the ALU, registers, and buses
Clock	Generates a regular pulse that synchronises all operations; clock speed (Hz) determines how many cycles per second
General-purpose registers	Small, fast storage holding operands and results during calculations

The ALU and CU together are the heart of instruction execution. The clock paces every operation — at each clock tick, one micro-operation (register transfer, bus transaction) occurs.

In addition to general-purpose registers, the processor has several dedicated registers with fixed purposes:

Register	Name	Purpose
PC	Program Counter	Holds the address of the next instruction to fetch
CIR	Current Instruction Register	Holds the instruction currently being decoded/executed
MAR	Memory Address Register	Holds the address to be read from or written to in memory
MBR / MDR	Memory Buffer / Data Register	Holds data being transferred to or from memory
Status register	Flags register	Holds condition flags (zero, carry, overflow, negative) set after ALU operations

The PC and MAR are connected to the address bus; the MBR is connected to the data bus.

The processor repeats the fetch-execute cycle continuously while running a program. Each instruction goes through three phases:

Fetch

1. Copy the address in PC → MAR (via the address bus)
2. Read the memory location at MAR → MBR (data bus brings instruction from RAM)
3. Copy MBR → CIR (the instruction is now loaded into the CPU)
4. Increment PC (so it points to the next instruction)

Decode

5. The CU decodes the instruction in CIR: determines the operation (opcode) and identifies the operand

Execute

6. The CU or ALU carries out the operation:
   • If a memory read: address → MAR; data → MBR → register
   • If arithmetic/logic: ALU takes operands from registers, stores result
   • If a branch: PC is overwritten with the target address

After execute, the cycle repeats — fetching the instruction at the new PC.

Worked example trace (instruction ADD R1, 200):

Step	Register/bus	Value
Fetch 1	PC → MAR	MAR = current instruction address
Fetch 2	Memory → MBR	MBR = encoded ADD R1, 200
Fetch 3	MBR → CIR	CIR = ADD R1, 200
Fetch 4	PC++	PC = next address
Decode	CU reads CIR	opcode=ADD, operand=200
Execute	200 → MAR; Memory → MBR	MBR = value at address 200
Execute	R1 = R1 + MBR	Result stored in R1

The instruction set is the complete set of machine code instructions a processor can execute. It is specific to the processor's architecture — code compiled for ARM will not run on x86 without recompilation (unless translated).

Each instruction has two parts:

$\underset{\text{what to do}}{\underbrace{\text{opcode}}}+\underset{\text{what to do it to}}{\underbrace{\text{operand}}}$

Part	Purpose	Example
Opcode	Identifies the operation	10110010 = LOAD
Operand	A value, address, or register reference	00001010 = memory address 10

The width of the opcode field limits how many distinct instructions the processor supports ($2^n$ opcodes from an $n$-bit opcode). The operand field width limits addressable memory.

The addressing mode specifies how the operand in an instruction is interpreted.

Immediate addressing

The operand is the data itself — the literal value to use.

ADD 5   ; add the number 5 to the accumulator

No memory access for the operand — the value is embedded directly in the instruction. Fastest mode.

Direct addressing

The operand is a memory address (or register name). The processor goes to that address to retrieve the actual data.

LOAD 200   ; load the value stored at memory address 200

Requires an additional memory access to fetch the operand. Slower than immediate but flexible — the data at the address can change.

Comparison:

Mode	Operand meaning	Memory accesses (for operand)	Speed
Immediate	Data value	0 — value is in the instruction	Fastest
Direct	Address of data	1 — fetch from that address	One extra access

1. Forgetting to increment the PC during Fetch

The PC is incremented during the Fetch phase (step 4), not after Execute. This is important because a branch instruction in Execute overwrites PC — the increment must have happened before the branch check. Questions that ask you to trace the FDE cycle step by step expect the PC increment during Fetch.

2. Confusing MAR and MBR

MAR holds an address; it is write-connected to the address bus. MBR holds data; it is connected to the data bus. If a question asks which register holds the data being read from memory, the answer is MBR — not MAR.

3. Stating the ALU executes all instructions

The ALU handles arithmetic and logical operations. The CU handles control flow (branches, register transfers, memory management). A STORE instruction is controlled by the CU, not the ALU.

4. Confusing immediate and direct addressing

In immediate addressing, the operand is the value (ADD 5 adds five). In direct addressing, the operand is a memory address (LOAD 200 loads whatever is stored at address 200). The question "what does the operand represent?" determines the mode.