Logic Gates to Circuits: Worked Practice

The Boolean logic spec lesson covers the three gates AQA 8525 requires: NOT, AND, and OR. Exam questions, however, rarely ask about a single gate in isolation. They present a circuit — several gates connected together — and ask you to complete a truth table or determine the output for given inputs.

This lesson is entirely worked practice. Every example uses only AND, OR, and NOT — no other gates are required for AQA 8525.

Quick gate reference:

Gate	Symbol	Rule
NOT	¬A	Flips the input: 0→1, 1→0
AND	A AND B	Output is 1 only if both inputs are 1
OR	A OR B	Output is 1 if at least one input is 1

When a circuit has more than one gate, work through it left to right — calculate the output of each gate before moving to the next.

Example circuit:

This circuit feeds A through a NOT gate first, then ANDs the result with B.

Inputs: A = 1, B = 0

Step	Operation	Value
1	NOT A	NOT 1 = 0
2	(NOT A) AND B	0 AND 0 = 0
Output		0

Inputs: A = 0, B = 1

Step	Operation	Value
1	NOT A	NOT 0 = 1
2	(NOT A) AND B	1 AND 1 = 1
Output		1

Always label intermediate values as you go. On an exam diagram, write the value on each wire after each gate — the examiner can see your working and may award method marks even if your final answer is wrong.

For a circuit with multiple gates, a truth table needs one column per intermediate value, not just one for each input and one for the output. This keeps you from making errors and shows the examiner your reasoning.

Example: Circuit for (A OR B) AND (NOT A)

Step 1 — identify all intermediate values:

• A OR B
• NOT A
• Final output: (A OR B) AND (NOT A)

Step 2 — build the table with all columns:

A	B	A OR B	NOT A	(A OR B) AND (NOT A)
0	0	0	1	0
0	1	1	1	1
1	0	1	0	0
1	1	1	0	0

Checking each row:

• Row 1: A=0, B=0 → OR=0, NOT A=1 → 0 AND 1 = 0 ✓
• Row 2: A=0, B=1 → OR=1, NOT A=1 → 1 AND 1 = 1 ✓
• Row 3: A=1, B=0 → OR=1, NOT A=0 → 1 AND 0 = 0 ✓
• Row 4: A=1, B=1 → OR=1, NOT A=0 → 1 AND 0 = 0 ✓

For a circuit with 2 inputs, there are always exactly 4 rows (2² = 4). For 3 inputs: 8 rows (2³ = 8). Never skip rows.

When a circuit has three inputs, the truth table has 8 rows. Write out all combinations of A, B, C systematically: treat it like binary counting — C alternates every row, B alternates every two rows, A alternates every four rows.

Example: (A AND B) OR (NOT C)

A	B	C	A AND B	NOT C	(A AND B) OR (NOT C)
0	0	0	0	1	1
0	0	1	0	0	0
0	1	0	0	1	1
0	1	1	0	0	0
1	0	0	0	1	1
1	0	1	0	0	0
1	1	0	1	1	1
1	1	1	1	0	1

Notice: the output is 1 whenever C = 0 (NOT C = 1), or when both A and B are 1 regardless of C.

AQA may give you a Boolean expression and ask you to draw or complete the circuit, or give you a circuit and ask you to write the expression.

Expression → Circuit:

Expression: (A AND B) OR (NOT B)

Read it as a recipe:

1. Feed A and B into an AND gate
2. Feed B into a NOT gate
3. Feed both outputs into an OR gate

Circuit → Expression:

Work left to right, naming each gate's output:

• Gate 1 (NOT on A): NOT A
• Gate 2 (AND on NOT A, and B): (NOT A) AND B
• If there were a further gate, continue chaining

The expression for the full circuit is: (NOT A) AND B

1. Applying NOT to the wrong input

NOT A AND B means (NOT A) AND B — the NOT applies only to A. A common error is interpreting it as NOT (A AND B), which gives a completely different truth table. If in doubt, add brackets.

2. Missing rows in the truth table

A two-input circuit has exactly 4 rows. A three-input circuit has exactly 8 rows. Skipping rows or duplicating rows will give a wrong answer even if your gate logic is correct.

3. Confusing AND and OR outputs

AND outputs 1 only when all inputs are 1 — it is the "strict" gate. OR outputs 1 when any input is 1 — it is the "generous" gate. Students frequently swap these under exam conditions.

4. Not using intermediate columns

Trying to calculate a multi-gate circuit "in your head" in one step leads to errors. Always add intermediate columns. They cost nothing and prevent mistakes.

5. Writing the expression in the wrong order

The expression should reflect the order gates are encountered from inputs to output — not the order you happened to notice them. Trace from left (inputs) to right (output).