CPU Architecture and the Fetch-Execute Cycle
Aligned to the OCR J277 specification
- Topic
- Systems architecture
- Level
- Intermediate
- Reading time
- 6 min
- Published
- 12 June 2026
- Updated
- 1 July 2026
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Key takeaways
- The fetch-execute cycle has three stages - Fetch, Decode, Execute - and repeats continuously while the computer is on; it has three stages, not two.
- MAR stores a memory address (where to look); MDR stores the actual data fetched; PC stores the address of the next instruction; ACC stores the result of the last ALU calculation.
- The CU (Control Unit) coordinates and controls the CPU but does not perform calculations - arithmetic and logic operations are carried out by the ALU.
- Cache is a small, fast memory store on or near the CPU chip; it is not RAM and not secondary storage - registers are fastest, then cache, then RAM.
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Key terms
- CPU
- The Central Processing Unit - the component that fetches, decodes, and executes program instructions, often called the processor.
- Fetch-execute cycle
- The continuous three-stage loop (Fetch, Decode, Execute) the CPU repeats to process every instruction in a program.
- ALU
- The Arithmetic Logic Unit - the part of the CPU that performs arithmetic operations (add, subtract) and logical operations (AND, OR, NOT, comparisons).
- CU
- The Control Unit - coordinates the operation of the CPU, decoding instructions and managing the flow of data between components.
- MAR
- Memory Address Register - holds the address of the memory location to be read from or written to during the fetch stage.
- MDR
- Memory Data Register - holds the actual data or instruction that has been fetched from memory or is about to be written to it.
- PC
- Program Counter - stores the memory address of the next instruction to be fetched, and is incremented after each fetch.
- ACC
- Accumulator - stores the result of the most recent arithmetic or logic operation performed by the ALU.
- Cache
- A small, extremely fast memory store on or near the CPU chip that holds recently used data and instructions to reduce the number of slower RAM accesses.
- Von Neumann architecture
- The design principle underlying most computers, where both program instructions and data are stored in the same main memory and fetched by the same CPU.
Frequently asked questions
MAR holds a memory address (where to fetch from). MDR holds the actual data or instruction fetched. PC holds the address of the next instruction to fetch. ACC holds the result of the most recent ALU operation. MAR and PC store addresses; MDR and ACC store data.
The Control Unit (CU) coordinates and manages the fetch-decode-execute cycle - it decodes instructions and tells other components what to do. The ALU (Arithmetic Logic Unit) actually performs arithmetic (add, subtract) and logical operations (AND, OR, NOT, comparisons).
Cache is a small, very fast memory store built into or near the CPU that holds frequently used data and instructions. RAM is separate, much larger, and slower. A cache hit means data is found in cache (fast); a cache miss means the CPU must fetch from the slower RAM.
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