The Fetch-Decode-Execute Cycle

Modern computers work by storing both data and instructions as binary in the same memory. The CPU (Central Processing Unit) reads instructions one at a time and executes them sequentially — this is the stored program concept.

Every program running on any device is a sequence of machine code instructions loaded into RAM. The CPU's job is to repeat one process indefinitely:

1. Fetch — retrieve the next instruction from memory
2. Decode — interpret what that instruction means
3. Execute — carry out the instruction

This loop is the fetch-decode-execute (FDE) cycle. It runs continuously from the moment a program starts.

The stored program concept means there is no architectural difference between code and data — both are binary numbers held in memory. This is why software can be updated without changing hardware.

The AQA 8525 spec requires understanding of these CPU components:

Component	Role
ALU (Arithmetic Logic Unit)	Performs arithmetic (add, subtract) and logic (AND, OR, NOT) operations
Control Unit (CU)	Directs the fetch, decode, and execute stages; sends signals to all other components
Clock	Generates regular electrical pulses that synchronise every CPU operation; measured in GHz
Registers	Ultra-fast storage locations inside the CPU holding single values needed immediately
Buses	Pathways carrying data (data bus), addresses (address bus), and control signals (control bus) between CPU and memory
Main memory (RAM)	Holds the instructions and data currently in use; much slower than registers

Named registers — helpful context, not required by AQA 8525: Many textbooks and teachers refer to specific registers by name. These are not assessed by name in AQA 8525, but knowing them helps follow the FDE cycle description:

Register	Name	Role
PC	Program Counter	Holds the address of the next instruction
MAR	Memory Address Register	Holds the address being read from or written to
MDR	Memory Data Register	Temporarily holds data travelling to or from memory
CIR	Current Instruction Register	Holds the instruction being decoded and executed
ACC	Accumulator	Holds the result of the most recent ALU operation

AQA 8525 requires you to know what a register is (fast, temporary CPU storage) and what the ALU, control unit, clock, and buses do — not to recall the names PC, MAR, MDR, CIR, or ACC from memory.

The fetch stage retrieves the next instruction from RAM and loads it into the CPU ready for decoding.

Step-by-step:

Step	What happens
1	The address in the PC is copied to the MAR
2	The MAR address is placed on the address bus; RAM is signalled to read
3	The contents of that memory location travel along the data bus into the MDR
4	The instruction is copied from the MDR into the CIR
5	The PC is incremented by 1 — it now points to the next instruction

The PC increment happens during fetch, not after execute. This means by the time the current instruction is being decoded, the PC is already pointing at the next one.

The address bus is one-directional (CPU → memory). The data bus is bidirectional — data can travel from memory to CPU (fetch/load) or from CPU to memory (store/write).

The Control Unit (CU) decodes the instruction held in the CIR to determine what operation is required and what data it applies to.

A machine code instruction has two parts:

Part	Name	Meaning
First bits	Opcode	Identifies the operation (e.g. ADD, LOAD, STORE, JUMP)
Remaining bits	Operand	The data value or memory address the operation uses

Example — an 8-bit instruction 00100101:

• Opcode 0010 → ADD
• Operand 0101 → the value 5 (or address 5, depending on addressing mode)

The CU interprets the opcode and sends control signals to the correct components: instructing the ALU to add, activating the memory interface to fetch more data, or updating the PC for a jump instruction.

No data travels between the CPU and RAM during the decode stage. Decode is entirely internal to the CPU.

The execute stage carries out the decoded instruction. The action taken depends entirely on the instruction type.

Instruction type	Component used	What happens
Arithmetic (ADD, SUB)	ALU	Calculation performed; result stored in ACC
Logic (AND, OR, NOT)	ALU	Bitwise operation performed; result stored in ACC
Load	Memory interface	Data fetched from RAM address (operand) into ACC
Store	Memory interface	Contents of ACC written to the RAM address in the operand
Jump (unconditional)	CU	PC is set to the address in the operand
Conditional jump	CU	PC is updated only if a condition is met (e.g. ACC = 0)

After execute completes, the cycle immediately begins again — the PC already holds the address of the next instruction (incremented during fetch), so no delay occurs between cycles.

Three hardware factors directly control how quickly a CPU completes FDE cycles.

1. Clock speed — measured in GHz. The clock synchronises all CPU operations; each tick of the clock drives one step forward in the cycle. A 4 GHz CPU completes up to 4 billion ticks per second. Increasing clock speed increases the number of FDE cycles completed per second.

2. Number of cores — a core is a complete, independent FDE processing unit. A quad-core CPU contains four cores, each capable of fetching, decoding, and executing simultaneously. Tasks that can be split across multiple cores (parallel workloads) benefit directly; single-threaded programs use only one core regardless.

3. Cache size — cache is ultra-fast memory built into the CPU chip, much faster than RAM. Recently used instructions and data are held in cache. A larger cache reduces cache misses (situations where the CPU must wait for a slow RAM fetch), keeping the FDE cycle running without stalls.

Factor	Effect of increasing	Limitation
Clock speed	More cycles per second	Heat generation; physical limits
Cores	Parallel execution	Software must be written to use multiple threads
Cache size	Fewer slow RAM accesses	Expensive to manufacture; diminishing returns

1. Confusing MAR and MDR

MAR holds an address (where to look in memory). MDR holds data (what was retrieved). They always work in sequence — MAR is loaded first, then the MDR receives the result.

2. Saying the PC increments after the execute stage

The PC increments during the fetch stage — before decode or execute begins. This is a deliberate design choice: decoding and execution can proceed while the PC already points to the next instruction.

3. Attributing arithmetic to the decode stage

The ALU performs arithmetic during the execute stage. Decode only interprets the opcode — no calculation happens during decode.

4. Listing RAM speed or RAM size as a CPU performance factor

The AQA 8525 spec lists three CPU performance factors: clock speed, number of cores, and cache size. RAM affects overall system performance but is not one of the three specified CPU factors — using it as an answer will not score the mark.

5. Saying more cores always makes the CPU faster

Additional cores only improve performance for multi-threaded workloads. A single-threaded program runs on one core regardless of how many cores the CPU has. More cores do not increase the speed of a single sequential task.