The Fetch-Decode-Execute Cycle

Modern computers work by storing both data and instructions as binary in the same memory. The CPU (Central Processing Unit) reads instructions one at a time and executes them sequentially — this is the stored program concept.

Every program running on any device is a sequence of machine code instructions loaded into RAM. The CPU's job is to repeat one process indefinitely:

1. Fetch — retrieve the next instruction from memory
2. Decode — interpret what that instruction means
3. Execute — carry out the instruction

This loop is the fetch-decode-execute (FDE) cycle. It runs continuously from the moment a program starts.

The stored program concept means there is no architectural difference between code and data — both are binary numbers held in memory. This is why software can be updated without changing hardware.

The AQA 8525 spec requires understanding of these CPU components:

Component	Role
ALU (Arithmetic Logic Unit)	Performs arithmetic (add, subtract) and logic (AND, OR, NOT) operations
Control Unit (CU)	Directs the fetch, decode, and execute stages; sends signals to all other components
Clock	Generates regular electrical pulses that synchronise every CPU operation; measured in GHz
Registers	Ultra-fast storage locations inside the CPU holding single values needed immediately
Buses	Pathways carrying data (data bus), addresses (address bus), and control signals (control bus) between CPU and memory
Main memory (RAM)	Holds the instructions and data currently in use; much slower than registers

Named registers — helpful context, not required by AQA 8525: Many textbooks and teachers refer to specific registers by name. These are not assessed by name in AQA 8525, but knowing them helps follow the FDE cycle description:

Register	Name	Role
PC	Program Counter	Holds the address of the next instruction
MAR	Memory Address Register	Holds the address being read from or written to
MDR	Memory Data Register	Temporarily holds data travelling to or from memory
CIR	Current Instruction Register	Holds the instruction being decoded and executed
ACC	Accumulator	Holds the result of the most recent ALU operation

AQA 8525 requires you to know what a register is (fast, temporary CPU storage) and what the ALU, control unit, clock, and buses do — not to recall the names PC, MAR, MDR, CIR, or ACC from memory.

The fetch stage retrieves the next instruction from RAM and loads it into the CPU ready for decoding.

Step-by-step:

Step	What happens
1	The address in the PC is copied to the MAR
2	The MAR address is placed on the address bus; RAM is signalled to read
3	The contents of that memory location travel along the data bus into the MDR
4	The instruction is copied from the MDR into the CIR
5	The PC is incremented by 1 — it now points to the next instruction

The PC increment happens during fetch, not after execute. This means by the time the current instruction is being decoded, the PC is already pointing at the next one.

The address bus is one-directional (CPU → memory). The data bus is bidirectional — data can travel from memory to CPU (fetch/load) or from CPU to memory (store/write).