Intermediate

Logic Gates and Circuits

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·A-Level Computer Science·AQA 7517·5 min
4.6.4 Logic gates

Logic Gates

Logic gates are the basic building blocks of digital circuits. Each gate takes one or more binary inputs (0 or 1) and produces a single binary output according to a fixed logical rule.

Six fundamental gates — you must know their truth tables and ANSI/IEEE symbols:

NOT (Inverter)

ANOT A
01
10

Boolean: or . Flips the input.

AND

ABA AND B
000
010
100
111

Boolean: . Output is 1 only when both inputs are 1.

OR

ABA OR B
000
011
101
111

Boolean: . Output is 1 when at least one input is 1.

XOR (Exclusive OR)

ABA XOR B
000
011
101
110

Boolean: . Output is 1 when inputs are different.

NAND (NOT AND)

ABA NAND B
001
011
101
110

Boolean: . AND followed by NOT. Output is 0 only when both inputs are 1.

NOR (NOT OR)

ABA NOR B
001
010
100
110

Boolean: . OR followed by NOT. Output is 1 only when both inputs are 0.

Reading and Drawing Circuits

Logic gates are connected in circuits to implement more complex Boolean functions. Each gate's output can feed into another gate's input.

Example circuit — two gates in sequence:

A ──┐
    AND ──── NOT ──── Output X
B ──┘

Boolean expression: — this is a NAND.

Completing a truth table for a circuit:

Circuit:

ABCA AND BX = (A AND B) OR C
00000
00101
01000
01101
10000
10101
11011
11111

Method: add intermediate columns for each gate's output, working left to right through the circuit. Never try to evaluate the whole expression in one column.

Half Adder

A half adder adds two single bits (A and B) and produces two outputs: a Sum bit and a Carry bit.

ABSum (A XOR B)Carry (A AND B)
0000
0110
1010
1101

Circuit: one XOR gate (Sum) and one AND gate (Carry), both taking A and B as inputs.

Why "half"? It has no carry-in input. It can add two bits but cannot chain together to add multi-bit numbers without modification.

Full Adder

A full adder adds two bits (A and B) plus a carry-in () — allowing it to be chained for multi-bit addition. It produces a Sum and a carry-out ().

ABSum
00000
00110
01010
01101
10010
10101
11001
11111

A full adder is built from two half adders and an OR gate. Chain full adders together to add two -bit binary numbers.

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D-type Flip-Flop

A D-type flip-flop is a simple memory element — it stores one bit. Unlike combinational logic (which depends only on current inputs), a flip-flop has state that persists until changed.

Behaviour:

  • Has a Data input (D) and a Clock input (CLK)
  • Output Q changes only on a rising edge (low→high transition) of the clock signal
  • At the rising clock edge: Q takes the value of D at that moment
  • Between clock edges: Q holds its previous value regardless of D
CLK edgeDQ (after edge)
Rising ↑00
Rising ↑11
No edgeanyQ unchanged

Why it matters: flip-flops are the fundamental building block of sequential circuits — registers, counters, memory cells. They allow circuits to remember and store information between clock cycles.

Common Exam Mistakes

1. Confusing XOR and OR

OR outputs 1 when at least one input is 1 (including when both are 1). XOR outputs 1 only when inputs are different — so XOR(1,1) = 0, not 1. For the half adder Sum, it is XOR, not OR.

2. Forgetting intermediate columns in circuit truth tables

For a three-gate circuit, you need at least one intermediate column. Trying to evaluate the whole expression in one step leads to errors — show your working gate by gate.

3. Confusing NAND and NOR

NAND = AND then NOT (output is 0 only when all inputs are 1). NOR = OR then NOT (output is 1 only when all inputs are 0). Remember: NAND's all-ones input gives 0; NOR's all-zeros input gives 1.

4. Confusing the half adder's Sum and Carry gates

Sum = XOR (adds the bits modulo 2). Carry = AND (set only when 1+1 overflows). The exam regularly asks you to state the Boolean expressions — memorise both.

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