Interrupts and Processor Performance

An interrupt is a signal sent to the processor that requests its immediate attention — it "interrupts" the current flow of execution to handle a higher-priority event.

Types of interrupts:

Type	Source	Example
Hardware	External device (I/O)	Keyboard key pressed; disk read complete; network packet arrived
Software	System call from a running program	Program requests OS service (open file, allocate memory)
Internal	CPU detecting an exceptional condition	Division by zero; illegal instruction; page fault

Interrupts make it possible for the CPU to respond to unpredictable external events without polling (repeatedly checking device status), freeing it to run other code between events.

An ISR (Interrupt Service Routine) is the handler code that runs in response to a specific interrupt. Each interrupt type has its own ISR — a function in the OS kernel that knows how to deal with that event.

• When a keyboard interrupt fires, the ISR reads the character from the keyboard buffer
• When a disk interrupt fires, the ISR signals that data is ready and resumes the waiting process

Interrupts are checked at the end of each FDE cycle, after the current instruction has fully executed.

Interrupt handling steps:

1. Check the interrupt flag (status register) at the end of Execute
2. If flag is set (interrupt pending): a. Save the current processor state — the volatile environment (PC, registers, status register flags) — to a stack in memory b. Load the ISR address into PC (redirect execution to the interrupt handler)
3. Execute the ISR (the next FDE cycles run ISR instructions)
4. At the end of the ISR: restore the saved state from the stack (PC, registers) — execution resumes from exactly where it was interrupted

Normal FDE loop:
  Fetch → Decode → Execute → Check interrupt?
                                     ↓ Yes
                              Save volatile state
                              PC ← ISR address
                              Run ISR
                              Restore volatile state
                              Resume normal execution

Why save the volatile environment? The ISR uses registers and may change the status flags. Without saving and restoring the interrupted program's state, the program would continue with corrupted register values after the ISR returns.

Several hardware characteristics determine how fast a processor executes programs:

Clock speed

• Measured in Hz (GHz for modern CPUs)
• Higher clock speed → more FDE cycles per second → faster instruction execution
• Doubling clock speed roughly doubles execution speed, within the same processor architecture

Number of cores

• A core is a complete FDE unit (ALU + CU + registers)
• A multi-core processor has multiple cores on one chip
• Multiple cores execute different threads/processes in parallel — genuinely concurrent
• A quad-core processor can run 4 threads simultaneously, but only if the workload is parallelisable

Cache memory

• A small, very fast memory bank between the CPU and main RAM
• L1 cache: smallest (KB), fastest, closest to the core — checked first
• L2 cache: larger (MB), slightly slower — checked if L1 misses
• L3 cache: larger still (MB–GB), shared between cores — checked if L2 misses
• If the required instruction/data is in cache (cache hit), the CPU avoids the slow main-memory access
• Cache effectiveness comes from locality of reference — programs tend to reuse the same instructions and nearby data repeatedly

Word length

• The number of bits a processor handles as one unit
• A 64-bit processor fetches, stores, and operates on 64-bit values in one instruction
• Wider word length: more data per instruction; more precision for numeric calculations

Address bus width

• Determines the maximum addressable memory: $n$-bit address bus → $2^n$ addressable locations
• A 32-bit address bus limits addressable RAM to 4 GiB regardless of how much is physically installed
• 64-bit address buses eliminate this practical constraint

Data bus width

• Determines how many bits are transferred per memory access
• A 64-bit data bus transfers 8 bytes per cycle; a 16-bit bus transfers 2 bytes
• Wider data bus reduces the number of memory access cycles needed to load large values or instructions

Factor	Increasing it improves	Trade-off
Clock speed	Instructions per second	Heat, power consumption
Cores	Parallel throughput	Only effective if software is multi-threaded
Cache size	Reduces memory latency	Cost, chip area
Word length	Data per instruction	Larger instruction encoding
Address bus width	Addressable memory	No direct performance impact
Data bus width	Data per memory access	Pin count, board complexity

1. Claiming the processor checks for interrupts during Execute

Interrupts are checked at the end of the FDE cycle (after Execute completes), not during it. The current instruction runs to completion before any interrupt is acknowledged.

2. Forgetting to save the volatile environment

A question asking "what happens when an interrupt is recognised?" must include: save the current state (PC and registers) to the stack, jump to ISR, restore state on return. Omitting the save/restore loses marks.

3. Stating more cores always means faster performance

More cores improve performance only for parallelisable workloads. A single-threaded program runs on one core — additional cores provide no benefit for that program.

4. Confusing clock speed with data bus width

Clock speed affects how many operations per second the processor performs. Data bus width affects how much data moves per operation. Both influence performance but in different ways — faster clock + narrow bus can still be bottlenecked by data transfer.