CPU Architecture and the Stored Program Concept

A computer system's core hardware consists of interconnected components that together execute programs.

Main components:

Component	Role
Processor (CPU)	Fetches, decodes, and executes instructions
Main memory (RAM)	Stores instructions and data currently in use
Address bus	Carries memory addresses from CPU to memory/devices
Data bus	Carries data between CPU, memory, and I/O controllers
Control bus	Carries control signals (read, write, clock, interrupt)
I/O controllers	Interface between the CPU/buses and external devices

The processor communicates with memory and I/O controllers through the system buses. Every read/write operation goes through this pathway.

A bus is a shared communication pathway — multiple components connected to the same set of wires.

Address bus

• Unidirectional — carries addresses from the CPU outward (to memory or I/O)
• Width determines how many distinct memory locations can be addressed: an $n$-bit address bus can address $2^n$ locations
• A 32-bit address bus addresses $2^{32}\approx 4$ GiB; a 64-bit bus addresses $2^{64}$ locations

Data bus

• Bidirectional — data flows both from memory to CPU (reads) and from CPU to memory (writes)
• Width determines how much data is transferred per cycle: an 8-bit data bus transfers 1 byte per cycle; a 64-bit bus transfers 8 bytes per cycle

Control bus

• Bidirectional — carries signals that coordinate operations
• Signal lines include: read/write, memory request, interrupt request, bus grant, clock signal, reset

Von Neumann architecture stores both program instructions and data in the same main memory, accessed over the same buses.

┌──────────┐    Address bus   ┌──────────┐
│          │ ─────────────── ▶│          │
│   CPU    │    Data bus      │  Memory  │
│          │ ◀──────────────▶ │ (data +  │
│          │                  │  code)   │
└──────────┘                  └──────────┘
        │
        └──── I/O Controller ──── Devices

Von Neumann bottleneck: instructions and data share the same bus to the same memory. The processor can either fetch an instruction or fetch/store data in one cycle — not both. This limits performance. Modern CPUs use caching to mitigate it.

Advantages:

• Single unified memory is simpler to design and program
• Memory can be dynamically allocated between code and data

Harvard architecture uses separate memory stores and buses for instructions and data.

         Instruction memory
              ┌────────┐
CPU ◀────────▶│  Code  │
│             └────────┘
│             Data memory
│             ┌────────┐
└────────────▶│  Data  │
              └────────┘

Advantages:

• Instructions and data can be fetched simultaneously (no bottleneck)
• Higher throughput for predictable workloads

Used in: digital signal processors (DSPs), microcontrollers, and embedded systems where deterministic performance matters.

Disadvantage: separate memories are less flexible — code space and data space are fixed; you cannot dynamically reallocate between them.

Each location in main memory has a unique address — an integer that the processor uses to identify exactly which byte (or word) to read or write.

• With an $n$-bit address bus: $2^n$ distinct memory locations are addressable
• Word length determines how much data is read/written per access

Worked example: a system with a 16-bit address bus and byte-addressable memory can address $2^{16}=65536$ different bytes (64 KiB).

Memory is organised as a flat array of addressable cells. The OS maps this into segments (code, stack, heap, data) for each running process.

The stored program concept (credited to von Neumann's work) states that:

Machine code instructions are stored in main memory. The processor fetches and executes them serially — one at a time, in sequence — unless a branch instruction redirects execution.

What this means in practice:

• A program is simply data in memory — it can be loaded, moved, and modified like any other data
• The same hardware executes any program by fetching different instructions from memory
• This is why general-purpose computers can run word processors, games, and databases on the same hardware

Before the stored program concept, computers were reprogrammed by physically rewiring circuits or replacing hardware components.

1. Confusing address bus and data bus

The address bus carries where to read/write (the memory address). The data bus carries what is being read/written (the actual value). Bus width has different implications: address bus width → addressable memory range; data bus width → amount of data per transfer.

2. Stating Harvard architecture is "better"

Harvard architecture has higher throughput for separate instruction/data access but is less flexible. Von Neumann's unified memory allows dynamic allocation and is simpler to implement. Neither is universally superior — the right choice depends on the application.

3. Confusing word length and address bus width

Word length (data bus width) controls how much data moves per cycle. Address bus width controls how many memory locations can be addressed. They are independent and often different values.

4. Misrepresenting the stored program concept

The stored program concept is not just "programs stored in memory" — the key insight is that instructions are data and can be treated as such. This makes reprogramming possible without hardware changes.